1. Field of Invention
This invention relates to a memory process and a memory structure made thereby, and particularly relates to a memory process that inhibits bending of buried conductive lines, and a memory structure fabricated with the memory process.
2. Description of Related Art
For purposes of increasing the channel length of transistors, fully utilizing the space of the substrate, increasing the distance between different levels of conductive lines and so forth, it is feasible to form buried conductive lines in the substrate.
For example, when the integration degree of DRAM increases beyond a certain level, the channel length of a traditional planar transistor is reduced to cause the short channel effects and so forth, and the shrinking of the device size also reduces the distance between word lines and bit lines to induce parasitic capacitance. By forming the word lines as buried lines in the substrate, the above issues are solved.
The buried word lines are electrically connected to conductive plugs by their end portions in a contact area. In a conventional process of forming buried word lines, the substrate material in an area is etched to form a cavity and define a contact area, the cavity is filled by a spin-on dielectric (SOD) film, a plurality of trenches are formed in the substrate in the array area and in the SOD film filled in the contact area by etching, a wet clean treatment is conducted, a gate oxide film is formed in each of the trenches, and then buried word lines are formed in the trenches.
Because the portions of the buried word lines in the contact area are anchored in a SOD film and the CD deviation of the trenches for containing the buried word lines caused by the wet clean treatment is large in the SOD film, the buried word lines show worse line bending in the contact area.